Two solutions are known for hardware conversion of polyphase resampling. The first solution is presently used for scaling of images in video processing chips. As clearly shown in FIG. 9, an input data sequence Din is input to a polyphase filter bank 1. In the illustrated example, the polyphase filter bank 1 outputs five output values on five lines, wherein the first four lines are input to a first multiplexer MUX1 and the last four lines of these lines are input to a second multiplexer MUX2. In addition, a phase value p, ranging from 0 to 1, is input to the circuit through a bus having N lines. The two most significant bits (MSB/Most Significant Bit) are input to a control input of both multiplexers MUX1, MUX2. Both output lines of the two multiplexers MUX1, MUX2 and the N−2 of the least significant bit (LSB/Least Significant Bit) of the phase value p are input to an interpolation circuit 2. The interpolation circuit 2 comprises a first adder 3, so that to the first input thereof is coupled to the output of the second multiplexer MUX2. At a second input of the first adder 3 is provided the sign-inverted output of the first multiplexer MUX1, so that the value provided from this output is subtracted. An output value of the first adder 3 is multiplied by the N−2 least significant bit of the phase value p by a multiplier 4. The result of the multiplication of the multiplier 4 is provided to an input of the second adder 5, and the output value of the first multiplexer MUX1 is input to another input of this adder for addition. A sequence of output values of the second adder 5 is input to a data output as output data Dout.
With a similar circuit arrangement, a fixed number of output values, usually 2K+1, is generated with sub-sample phases at an equal interval (0 . . . 1). One pair of the samples adjacent to each other will be selected depending on the desired phase. The output sample, provided as a data value of the output data Dout, is obtained with a linear interpolation between these values. Accordingly, when K=2, there are five output values in the illustrated embodiment which have the phases 0, ¼, 2/4, ¾, 1. The first phase 0 corresponds as a first of these phase values p to the current sample of the input data Din and the phase 1 of the next sample. The phases in between, or intermediate phases, are generated by means of a hierarchical treelike structure by the filter banks. In such a case, only symmetrical half band filters with a constant coefficient are used. FIG. 9 shows a circuit arrangement for the case when K=2.
According to the second solution, shown in a simplified manner in FIG. 10, two interpolation FIR filters (FIR: Final Impulse Response) are used with a variable coefficient. The output sample is determined by linear interpolation between two filter output values.
Coefficient formulations in this case are predefined for a predetermined number of equidistant phases, usually 2K+1. Depending on the output phase, two adjacent coefficients are selected by means of multiplexers and input to the interpolation filter. FIG. 10 again shows the case when K=2.
The input data Din are in this case input to two interpolation FIR filters 6, wherein six first coefficients C0-1, C1-1, . . . , C5-1 of a 8×4:1 multiplexer 7 are input as coefficients to the first of the interpolation FIR filter 6. Six further coefficients C0-0, C1-0, . . . , C5-0 are input to the second interpolation FIR filter 6. In this formulation, the two most significant bits (MSB) of the phase value m, which is again input via a bus with n lines, to the corresponding twelve inputs of the multiplexer 7. The output values of both interpolation FIR filters 6 are again input, as shown in the case of the circuit arrangement indicated in FIG. 9, to an interpolation circuit 2. In addition, the least significant bits N−2 of the phase value p are again input to the interpolation circuit 2.
Nevertheless, both circuit arrangements have disadvantages. According to the first solution shown in FIG. 1, only two of the 2K+1 polyphase values are used for a given output phase in order to carry out linear interpolation. However, both output values are not used. In spite of that, all the output values must be generated so as to have all possible phase values p available in the range of [0 . . . 1]. An increase in the number of polyphase output values, which would increase the precision of interpolation, would make the solution even more ineffective. A particular disadvantage is also the fact that a similar hierarchical filter bank structure cannot be easily scaled for different numbers of polyphase output values. The disadvantage of the second solution shown in FIG. 10 is that the multiplier and the adder of the interpolation filter must be duplicated. A disadvantage shared by both solutions is that when several channels are to be interpolated in parallel to each other, a linear interpolation must be carried out separately for each individual channel.
The task of the present invention is to propose a device and a method for polyphase resampling, which enables a reduced expense, while at the same time achieving an equally good or better precision.
Arrangements provided with one FIR filter and used as a continuously variable digital delay element are generally known from C. W. Farrow, Continuously Variable Digital Delay Element, AT & T, Middletown, N.J. 07748, 1988 IEE. Such an architecture, however, is used only for the calculation of coefficients for a Lagrange polynomial interpolation, and it is also referred to as Farrow structure.
This task is solved by a device for polyphase resampling which has the characteristics according to claim 1, or by the method for polyphase resampling having the characteristics according to claim 10. Advantageous embodiments are the subject of dependent claims.